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Lattice Semiconductor
(c) Dual-Channel: Inputs are sampled in every Rate clock cycles:
clk
Functional Description
din
x(0)
u (0)
x(1)
u (1)
x(2)
u (2)
x(3)
u (3)
x(4)
u (4)
i b start
i b start
rfi b
do u t
y x (0)
y u (0)
y x (1)
y u (1)
y x (2)
y u (2)
y x (3)
y u (3)
y x (4) y u (4)
y x (5)
o b start
o u t v alid
2* Rate Clock Cycles
2* Rate Clock Cycles
2* Rate Clock Cycles
2* Rate Clock Cycles
Filter Latency+ 2* Rate Clock Cycles
(d) Dual-Channel: Inputs are sampled in every 2* Rate clock cycles:
clk
din
x(0)
u (0)
x(1)
u (1)
x(1)
u (1)
i b start
inp v alid
rfi
do u t
y x (0)
y u (0)
y x (1)
y u (1)
y x (2)
y u (2)
y x (3)
y
o b start
o u t v alid
4* Rate Clock Cycles
Filter Latency+ 4* Rate Clock Cycles
4* Rate Clock Cycles
IPUG42_02.6, August 2010
17
Cascaded Integrator-Comb (CIC) Filter User’s Guide
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